The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical modern circuits contain hundreds of thousands or millions of individual pieces or "cells." Such a design is much too large for a circuit designer or even an engineering team of designers to manage effectively manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system that designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this high level design language description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. The generic netlist can be translated by the EDA system into a lower level technology-specific netlist based on a technology-specific library that has gate-specific models for timing and power estimation. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a graph structure having nodes which are connected to each other with signal lines. The netlist is typically stored in computer readable media within the EDA system and processed and verified using many well known techniques. The netlist is then used to generate a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test for manufacturing defects. With current technology, as the number of gates and transistors increase, the time which an ASIC spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest ASIC designs. In addition, as more complex systems-on-a-chip devices proliferate, which integrate complex logic units (e.g., integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis and testing process involves designing ASICs and other complex integrated circuits for inherent testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is well known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. On the other hand, issues concerning observability deal with facilitating the capturing the output of the circuitry.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its "mission mode" circuitry, while the portions added to the integrated circuit to facilitate testability are called "test mode" circuitry or DFT implementations. The resultant circuit, therefore, has two functional modes, mission and test.
An exemplary flow chart diagram of a typical design automation process 100, including a DFT process, is shown in FIG. 1. The process 100 described with respect to this flow chart is implemented within a computer system in a CAD environment. Within the process 100, a circuit designer first generates a high-level description 105 of a circuit in a hardware description language such as VHDL or Verilog. The high-level description 105 is then converted into a netlist 115 by using a computer implemented synthesis process 110 such as the "Design Compiler" available from Synopsys, Inc., of Mountain View, Calif. A netlist 115 is a description of the electronic circuit which specifies what cells compose the circuit and which pins of which cells are to be connected together using interconnects ("nets"). At this point the netlist 115 consists of "mission mode" circuitry.
At block 120, a constraint-driven scan insertion process is performed to implement testability cells or "test mode" cells into the overall integrated circuit design. In this process 120, memory cells of the netlist 115 are replaced with scannable memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In addition, process 120 performs linking groups of scannable memory cells ("scan cells") into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 120 is a scannable netlist 125 that contains both "mission mode" and "test mode" circuitry.
Test vectors for testing the integrated circuit can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on the parameters, interconnections, etc., of the scannable netlist 125. Thus, at block 130, a specific procedure known as combinational ATPG "design rule checking" (DRC) is applied to determine whether combinational ATPG tools properly understand and interpret the parameters, interconnections, etc. of the scanned netlist 125. Combinational ATPG DRC 130 is very restrictive with regard to the parameters, formats, etc., of the scannable netlist 125. For instance, prior art combinational ATPG design rule checkers rejected netlists which contained multiple capture events. Netlists containing non-scan cells were also rejected by prior art combinational ATPG design rule checkers. Such netlists could not be properly processed by prior art combinational ATPG compilers.
If the scannable netlist 125 meets the requirements of combinational ATPG DRC 130, the scanned netlist 125 is passed to block 140 for combinational ATPG processing. The result of this combinational ATPG processing 140 is a test program 145 adapted for application to automatic test equipment (ATE) 160. If scannable netlist 125 does not pass combinational ATPG DRC at block 130, a less restrictive procedure known as sequential ATPG processing 150 is applied in place of combinational ATPG processing 140. However, sequential ATPG processing 150 has a disadvantage in that it is far more complex, expensive and time consuming than combinational ATPG processing 140.
One way to avoid sequential ATPG processing 150 is to repeat scan insertion process 120 using different test constraints to generate a new scannable netlist. The new netlist is then processed for combinational ATPG DRC 130. If combinational ATPG DRC 130 is passed, combinational ATPG processing 140 is applied. If not, the scan insertion process 120 may have to be repeated again. This approach is also disadvantageous because each modification requires new, time-consuming, compile processes. The additional compile processes delay the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the additional compiles will generate a scannable netlist satisfying combinational ATPG DRC in step 130.
Another way to avoid sequential ATPG processing 150 is to relax the constraints of the combinational ATPG DRC 130 to receive netlists containing multiple skewed events and non-scan cells. In those cases, scan cells are transformed into equivalent combinational circuit models based on their respective observability and controllability during combinational ATPG processing 140. In addition, non-scan cells of the scannable netlist 125 are replaced with "force-to-X" logic models. That is, the outputs of the non-scan cells are presumed to be "X" or "don't care" regardless their actual logic states. This approach is significantly faster and more efficient than sequential ATPG processing 150, and is particularly effective in "almost full-scan" designs (e.g., designs having 99% scan cells and 1% non-scan cells). However, as non-scan cells are replaced with "force-to-X" logic models, fault coverage of the test patterns thus generated would be significantly compromised.
Thus, what is needed is a method and system for testing scan based sequential circuits that contain non-scan cells using combinational ATPG techniques. Additionally, what is further needed is a method and system for providing increased fault coverage for test vectors generated by combinational ATPG. The present invention provides these advantages.